As integrated circuit (IC) technologies are continually progressing to smaller technology nodes, such as a 32 nm technology node and below, simply scaling down similar designs used at larger nodes often results in inaccurate or poorly shaped device features due to the resolution limit of conventional optical lithography technology. Examples of inaccurate or poorly shaped device features include rounding, pinching, necking, bridging, dishing, erosion, metal line thickness variations, and other characteristics that affect device performance. One approach to improving image printing quality on a wafer is to use restrictive design rules (RDR) in IC layout designs. An exemplary IC layout according to RDR includes parallel line patterns extending in the same direction and spaced by a pattern pitch. The line width and pattern pitch are designed so as to improve image printing quality by utilizing constructive light interference.
However, in a large scale IC, not all patterns are designed according to the same design rules. For example, an IC may include both logic circuits and embedded static random-access memory (SRAM) cells. The SRAM cells may use smaller pitches for area reduction, while the logic circuits may use larger pitches. For another example, an IC may include multiple off-the-shelf macros, each of which has been laid out according to its own set of RDRs. In such ICs, multiple layout blocks may be used. Each layout block is designed according to a set of RDRs and different layout blocks may use different RDRs. A space is provided between any two layout blocks to accommodate printing inaccuracy such as line end rounding, as well as to meet certain spacing requirements for IC manufacturing. This space becomes a concern when greater device integration is desired.